1. Technical Field
The present disclosure relates to a time-to-digital converter (TDC). More particularly, the present disclosure relates to a pipeline TDC.
2. Description of Related Art
A time-to-digital converter (TDC) is one of important techniques in development of integrated circuits, and the TDC is widely used in communication chips, biomedical chips and measurement chips. For example, in a digital phase-locked loop (DPLL) of the communication chip, a TDC with a high resolution is used to reduce in-band phase noise of the loop. If the phase noise is required to be less than 100 dB c/Hz, the resolution is required to be 6 ps. However, design of a high resolution TDC is a great challenge.
Design of the high resolution TDC mainly faces three main problems: (1) whether a resolution of an advanced process circuit is high enough; (2) whether a dynamic-range of circuit operation can be increased; (3) whether it can be avoided to use a complex approach or a super high-speed clock to process data. Therefore, the above three problems has to be balanced to meet a system application and power requirements. Regarding the resolution, it is one of important standards of the DPLL.
In a U.S. Pat. No. 7,205,924, a Vernier TDC is used, and delay buffers are added to two paths of a high-speed clock (2 GHz) and a reference clock (26 MHz). A resolution of such structure is limited by the delay buffers, and highly relates to a semiconductor process, which can only provide a resolution of 20 ps in a CMOS 90 nm process.
According to an article “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue” (IEEE JSSCC, vol. 43, no. 4, pp. 769-777, April 2008) authored by Minjal Lee and Asad A. Abidi et al., when the resolution is not enough, a time residue is first amplified by a calibrated time amplifier (TA), and then a further analysing is performed, so that the resolution can reach 1.25 ps. Such structure requires a rather complex calibration circuit to calibrate the time amplifier, and a main problem thereof is that an accurate time amplification gain of time cannot be obtained according to a feedback approach as that does of a voltage, so that a non-ideal effect of the time amplifier is an intractable problem.
If a gated ring oscillator (GRO) is used to improve the resolution, such as TDCs disclosed in a U.S. Pat. No. 6,754,613 and a U.S. Patent Application No. 2008/0069292 A1, etc., the problem of the time amplifier is unnecessary to be handled. However, such structure requires rather high oscillation frequency and consumes rather great power (about 10 times) to obtain a relatively high resolution (for example, 1 ps).
Moreover, according to an article “A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques” (IEEE JSSCC, vol. 44, no. 3, pp. 824-834, March 2009) authored by E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto et al., a calibrated delay circuit is used to generate a little difference between a plurality of high-speed clocks, so as to increase the resolution. For example, the calibrated delay circuit can sample one more times in one of every 5 high-speed clock semi-periods, and the resolution thereof can be 7.9 ps. However, a shortage of such structure is that if the dynamic-range of the circuit operation is increased, i.e. a frequency of the high-speed clock is decreased, a plurality of the high-speed clocks cannot be used to generate the difference, so that the resolution is decreased.